1. Field of the Invention
The present invention relates to a charge pump circuit, particularly to prevention of the latch-up of the charge pump circuit.
2. Description of Related Art
A charge pump circuit generating from a single power supply voltage positive and negative output voltages whose absolute values are larger than the supply voltage is widely used. An example of such a charge pump circuit, for example, is disclosed in Japanese Unexamined Patent Application Publication No. 6-165482. Referring to FIG. 6, there is illustrated a conventional charge pump circuit 100 including a positive voltage generating circuit 110 and a negative voltage generating circuit 120. Connecting a power source between an input terminal 1 and a ground terminal 2 to supply power source voltage VDD causes the positive voltage generating circuit 110 to generate a positive voltage (+2VDD) twice of the power source voltage VDD. The positive voltage (+2VDD) is provided to the negative voltage generating circuit 120. The negative voltage generating circuit 120 generates a negative voltage (−2VDD) twice of the power source voltage VDD using the positive voltage (+2VDD). The positive voltage (+2VDD) is output between a positive output terminal 3 and the ground terminal 2 and the negative voltage (−2VDD) is output between a negative output terminal 4 and the ground terminal 2.
The positive voltage generating circuit 110 includes the switches S11–S14 and the capacitors C11, C12. The capacitor C11 is charged with the power source voltage VDD from the input terminal 1 when the switches S11, S12 are on and the switches S13, S14 are off. Subsequently, the switches S11, S12 are turned off and the switches S13, S14 are turned on to discharge the capacitor C11. The capacitor C12 is charged with the power source voltage VDD plus the charged voltage of the capacitor C11. Switching alternatively the switches S11, S12 and the switches S13, S14 charges the capacitor C12 and the positive voltage generating circuit 110 supplies the positive voltage (+2VDD) twice of the power source voltage VDD to the negative voltage generating circuit 120 and the positive output terminal 3.
The negative voltage generating circuit 120 includes the switches S21–S24 and the capacitors C21, C22. The positive voltage supplied from the positive voltage generating circuit 110 charges the capacitor C21 when the switches S21, S22 are on and the switches S23, S24 are off. Subsequently, when the switches S21, S22 are turned off and the switches S23, S24 are turned on, the capacitor C21 discharges and the capacitor C22 is charged. A switching alternatively the switches S21, S22 and the switches S23, S24 is repeated as such to charge the capacitor C21 allowing the negative voltage generating circuit 120 to provide the negative output terminal with the negative voltage twice of the power source voltage VDD (−2VDD).
FIG. 7 illustrates an example of the charge pump circuit 100 using MOS transistors for the switches S11–S14 and S21–24. Enhancement P-channel MOS transistors designated as M11, M13, M14, M21 correspond to the switches S11, S13, S14, S21, respectively. Enhancement N-channel MOS transistors designated as M12, M22–24 correspond to the switches S12, S22–24, respectively. The gates of the MOS transistors are designated as G11, G12, G13, G14, G21, G22, G23, and G24, respectively. In the positive voltage generating circuit 110, when the MOS transistors M11, M12 are turned on and the MOS transistors M13, M14 are turned off, the capacitor C11 is charged with the power source voltage VDD. When the MOS transistors M11, M12 are turned off and the MOS transistors M13, M14 are turned on, the capacitor C11 is discharged and the capacitor C12 is charged with the power source voltage VDD plus the voltage of the charged capacitor C11.
In the negative voltage generating circuit 120, when the MOS transistors M21, M22 are turned on and the MOS transistors M23, M24 are turned off, the capacitor C21 is charged. Subsequently, when the MOS transistors M23, M24 are turned on and the MOS transistors M21, M22 are turned off, the capacitor C22 is charged with the charges from the discharged capacitor C21. An electrostatic discharge protection diode Di is connected between the input terminal 1 and the positive output terminal 3.
The charge pump circuit 100 illustrated in FIG. 7 is integrated in a single semiconductor substrate with external capacitors. For example, using a P-substrate, each N-channel MOS transistor M12, M22–24 is configured with the back gate of the P-substrate and the source/drain of N-regions on the P-substrate. Each P-channel MOS transistor M11, M13, M14, M21 is consisted of the back gate of N-well on the P-substrate and the source/drain of P-regions in N-well. Hence, the voltage of the P-substrate is the voltage of the negative output terminal 4. The diode Di configured with the cathode of N-well on the P-substrate 11 and the anode of a P-region in the N-well.
It has now been discovered that the charge pump circuit 100 integrated in a semiconductor substrate has parasitic transistors FIG. 8 depicts the main part of the charge pump circuit 100. The MOS transistor M12 has the source/drain of the N-regions 12, 13. The gates of the MOS transistors are designated as G12 and G13, respectively. There are formed N-well 14, 15 on the P-substrate. P-regions 16, 17 formed in the N-well 14 form the source/drain of the MOS transistor M13. The P-region 18 formed in the N-well 15 constitutes the diode Di. The N-region 12, that is the source of the MOS transistor M12, is grounded. The N-region 13, that is the drain of the MOS transistor M12, is connected to the P-region 17 that is the drain of the MOS transistor M13. The P-region 16, that is the source of the MOS transistor M13, is connected to the input terminal 1. The N-well 14 is connected to the positive output terminal 3. The P-substrate 11 is connected to the negative output terminal 4.
At the moment of applying the power source voltage VDD to the input terminal 1 on the start-up of the charge pump circuit 100, forward current flows between the P-region 18 constituting the diode Di and the N-well 15 or between the P-region 16 constituting the MOS transistor M13 and the N-well 14. As a result, the positive output terminal voltage is raised toward VDD.
Since the voltage of the P-substrate 11 is floating, a parasitic PNP-transistor Qp1 which is consisted of the P-region 18, the N-well 15 constituting the diode Di and the P-substrate 11 is turned on. Also turned on is a parasitic PNP-transistor Qp1 which is consisted of the P-region 16 constituting the MOS transistor M13, the N-well 14 and the P-substrate 11. As a result, the P-substrate 11 voltage is raised toward VDD.
The rise of the P-substrate voltage turns on a parasitic NPN-transistor Qp2 which is consisting of the N-well 15 constituting the diode Di, the P-substrate 11 and the grounded N-region 12 which is the source of the MOS transistor M12. It also turns on a parasitic NPN-transistor Qp2 consisting of the N-well 14 constituting the MOS transistor M13, the P-substrate 11 and the grounded N-region 12.
As a result, the parasitic transistors Qp1, Qp2 operate as a thyristor. A large current flows between the input terminal 1 and the ground terminal 2 prohibiting the start of the charge pump circuit 100. For starting the charge pump circuit 100 normally, it is required to connect a schottky diode between the input terminal 1 and the positive output terminal 3 or between the negative output terminal 4 and the ground terminal 2. The schottky diode has the forward voltage Vf smaller than the forward voltage between the P-region 16, 18 and the N-well 14, 15 or between the P-substrate 11 and the N-region 12 to keep the parasitic PNP-transistors Qp1 off. It, however, leads to increase of external parts and implementation area.